Sintered Nanocopper Paste for High-Performance 3D Heterogeneous Package Integration

Fifth-generation (5G) communications have been driving major package innovations to enable low-loss interconnects between the integrated circuits (IC) and other system components such as antenna arrays. Antenna-in-package with three-dimensional (3D) or double-side component is widely pursued as the front-up architecture to realize this vision. The interconnect height and losses are critical parameters in these 3D package structures. Copper sintering paste is emerging as an ideal candidate to replace solders for both off-chip and on-package interconnects because of the resulting higher electrical conductivity and relatively simple manufacturability with additive processes. This article focuses on computational modeling, optimization of sintering conditions, and electrical conductivity measurements of highly conductive copper paste to verify the proposed model. The model is based on two-particle sintering theory, which describes the neck growth evolution of copper paste at the initial stage of sintering. The neck-growth model shows good consistency with the measured neck size of copper, and hence can be used to provide guidelines for the sintering conditions of copper paste. The celectrical conductivity measurements suggest that the copper paste sintered at 260°C for 30 min shows a electrical conductivity of 1.4 × 10 7 S/m, which is 82% higher than that of solder. In addition, this article investigates the potential of copper paste interconnect technology in high-frequency applications such as in 5G millimeter-wave communications. The transmission lines patterned with the copper paste show good correlation with simulated results in the millimeter-wave frequency band. The high-frequency characterization also indicates that the copper paste enables simple circuit patterning, offering equivalent signal losses with plated copper. The detailed analyses discussed in this article suggest the eligibility for multi-applications of copper sintering paste in IC packaging.