Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level

In this article, we design a novel cell-level power-analysis countermeasure, named fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic. The countermeasure further acts as a cell-level $V_{DD}$ randomizer, making it a strong candidate for implementing algorithmic countermeasure and exp...