Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2021)

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摘要
In this article, we design a novel cell-level power-analysis countermeasure, named fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a cascade voltage logic. The countermeasure further acts as a cell-level $V_{DD}$ randomizer, making it a strong candidate for implementing algorithmic countermeasure and exp...
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关键词
Integrated circuit modeling,Power dissipation,Power demand,Logic gates,MOS devices,Cryptography
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