PMOS SiGe epitaxial growth process improvement to increase Yield and Throughput

In this paper, we present the development of a new 14nm SiGe process that is designed to improve with-in-wafer uniformity to eventually improve Electrical parameters, parametric limited yield and overall average yield. In addition we showed that throughput has also improved. The methods presented involved adding cross-flows of same process gases and optimizing the flows, temperature, power and time. By doing so, significant improvement in the WIW uniformity (growth and dopant concentration) and improvement in Defects were observed. This WIW uniformity led to significant improvements in various Electrical Test parameters as well as yield.