A high throughput PMOS Source-Drain process optimized within FINFET architecture for high volume chip manufacturing

Developed a novel multi-layered eSiGe film on FINFET architecture to increase PMOS performance by optimizing within wafer (WiW) uniformity for lateral growth and Boron concentration. The new process reduced growth related defect issues on large die products and excess abnormal growth defects to improve yield and reliability of latest semiconductor chips.