Using launch-on-capture for testing BIST designs containing synchronous and asynchronous clock domains

WangLaung-Terng,WenXiaoqing,WuShianling,FurukawaHiroshi, ChaoHao-Jan,SheuBoryau,GuoJianghao,JoneWen-Ben

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（2010）

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摘要

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing mul...

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