Semi-analytical Path Delay Variation Model with Adjacent Gates Decorrelation for Subthreshold Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2021)

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摘要
The subthreshold circuit is a practical design style for the ultralow-power applications, but its timing estimation is a challenge due to the increasing local variation effects. The delay variation of adjacent gates is not independent because of input slew variation caused by the precedent gate, so their correlation effects are difficult to model and estimate. This article proposes a semi-analytic...
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关键词
Delays,Logic gates,Load modeling,Correlation,Computational modeling,SPICE,Threshold voltage
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