FPGA HW/SW Codesign Approach for Real-time Image Processing Using HLS

Real-time constraint is one of the most common challenges found in many critical embedded applications, namely image and video processing. However, software tools such as Matlab and general purpose microprocessor are not suitable for deals with such a problem. Recently, FPGA reconfigurable circuit with its HLS software tools is become a very promising technology to be widely used in many applications encompassing all aspects and requirements of embedded system. This paper presents the implementation of morphological image operation including dilation, erosion and linear filtering. The implementation method is based on Hardware/Software (HW/SW) codesign approach using High Level Synthesis (HLS) tools, Xilinx Vivado 15.2 and SDK 15.2. Zedboard FPGA platform with Zynq device is used for this work in which is connected to a PC through an Ethernet link. Captured image by Webcam is transmitted to the FPGA for processing and will be then returned to the PC to be displayed on the IHM interface, in real-time. Experimental results demonstrate the feasibility of the proposed approach and it can be extended for other applications.