Protecting scratchpad memory addresses against soft errors

Scratchpad memories (SPMs) are intensively utilized in modern embedded processors where a demand on improving reliability without compromising performance-predictability and area/power efficiency is on rise. Our observations imply that one target for this reliability improvement is to combat ever increasing threats of multiple bit upsets (MBUs) occurring in the SPM addresses as well as multiple event transients (METs) happening in the SPM address decoders (SADs). This paper proposes two masking techniques that protect SPM addresses in their lifespan across multiple on-chip structures prone to MBU/MET errors. The strategy behind both techniques is to replicate narrow-width SPM addresses at compile time, and to mask errors at the SAD stage. The first technique is triplication of SPM addresses (TSA), and using a triplicated SAD. For the processors having limited memory address widths, the second technique uses the concept of redundant residue number system to provide a residual replication of SPM addresses (RRSA), and a residually replicated SAD. Simulation results showed that interleaving the retained bits between replicas/residues extends error masking coverage of TSA and RRSA from 86% and 78% to 91% and 97% with no performance loss, while imposing only 0.23% and 0.11% power and 0.02% and 0.01% area to the processor.