Lithography solutions for a 0.35 mu m 25V PDMOS technology

Lateral extended-drain MOS transistors (DMOS) are very sensitive to the well and Reduced Surface Field (RESURF) implant critical dimensions (CDs) as well as the layer-to-layer alignment (overlay). The photoresist that is used for the well and RESURF implants of the DMOS was originally highly dependant on reticle transmission (RT). This caused significant variability in the P-channel DMOS (PDMOS) performance, while the N-channel DMOS (NDMOS) performance remained stable. The lithography solutions to improve the robustness of the DMOS structures are discussed in this paper.