In-Situ Boron Doped SiGe Epitaxy Optimization for Finfet Source/Drain

In-situ Boron doped embedded SiGe epitaxy has been widely used for CMOS source/drain in advanced technology nodes, from its introduction in planar devices to its more recent application in FinFETs. Compared to planar technology, FinFETs have the benefit of an improved short channel effect, which enables significantly higher in-situ doping level for lower contact resistance. This work explores the source/drain expitaxy design differences between planar and FinFET transistors, and how the in-situ doped epitaxy process can be optimized to address the call for a higher doping level in the FinFET source/drain. Specifically, we observe a competing relationship between germanium and boron incorporation -- increasing Ge incorporation generally lowers boron doping, and increasing boron incorporation generally lowers Ge. Moreover, our work shows that the limit of boron doping can be boosted by increasing Ge percentage, and furthermore a Si-Ge-B phase diagram is proposed based on this experimental data. Defective epitaxy is observed outside of the soluble region of the phase diagram, featuring Boron-rich incoherent phase or Boron segregation. Finally, we present device data that show the performance benefit when Ge% and boron is optimized according to the phase diagram, characterized by lower Ron and higher drive current.