Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications

In this paper, a power minimizing strategy from a system- and circuit-perspective is developed for low-power reconfigurable multi-mode sigma-delta modulators. An experimental low-power modulator is designed for multi-mode systems with second- and fourth-order cascaded architectures. Several criteria are obtained to investigate the stability of the cascaded sigma-delta architecture. The proposed modulator can adapt to different system specifications with switchable stages and double-sampled techniques for better power efficiency. A test modulator chip is demonstrated with 0.13 m CMOS technology. With the proposed strategy, the simulation results indicate that the designed fourth-order cascaded modulator will dissipate powers of 4.2, 11.3, and 20.2 mW and obtain a figure-of-merit (FoM) of 169, 149, and 157 dB at a supply voltage of 1.2 V for bandwidths 100kHz, 2 MHz, and 20 MHz, respectively.