Physical Study of SiC Power MOSFETs Towards HTRB Stress Based on C-V Characteristics

The quality of the gate-oxide and Oxide/SiC interfaces is one of the crucial issues in the implementation of silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in the industrial power electronic applications. The main goal of this work is to investigate the gate-oxide integrity and to understand the basic phenomena involved on 4H-SiC MOSFET by the mean of Capacitance-Voltage (C-V) characterizations. The paper presents HTRB (High Temperature Reverse Bias) test results on the second and third generations of SiC MOSFETs. The C-V measurements are compared to physical simulation results. The good agreement between 2D numerical simulations and measurements suggests failures related to acceptor interface traps and doping concentration variations.