28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications

For energy-constrained multi-sensing IoT devices, ultra-low-power queueing is one of the critical event-driven design challenges to capture low-speed sensing data with various sampling frequencies. In this paper, 0.3V 1W2R subthreshold FIFO memory is proposed for ultra-low-voltage operations using Schmitt-Trigger (ST) 12.5T SRAM bit-cell, ripple bitline structure and cross-point data-aware write wordline scheme. The ST 12.5T memory bit-cell not only increases hold static noise margin (HSNM) but also eliminates write half-select disturbance for robust sub-threshold operation. Secondly, an adaptive timing tracing circuitry and negative bit-line circuits are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bitline structure divides the bitline into several segments for ultra-low-voltage operations. Thus, the access time can be reduced apparently. Finally, a 4kb sub-threshold FIFO memory with the proposed multi-port ST 12.5T bit-cells is implemented by UMC 28nm HKMG technology. The proposed FIFO memory can execute one write and two read operations simultaneously for multisensor IoT applications. The average power and maximum write frequency are 4.01μW and 780kHz at 0.3V, respectively.