A Full-Duplex Receiver Leveraging Multiphase Switched-Capacitor-Delay Based Multi-Domain FIR Filter Cancelers

Wideband self-interference cancellation (SIC) in full-duplex (FD) radios requires the achievement of large delays to accurately emulate the SI channel. However, compact, power-efficient, low-loss/noise nanosecond-scale delays are extremely challenging to achieve on silicon. Passive LC-based approaches are area intensive, whereas active approaches are power hungry and noisy. In this work, we presented a technique which leverages switched-capacitor circuits with multiphase clocking to obtain large on-chip delays with low area and power consumption. This technique is demonstrated in a FD receiver with time-interleaved switched-capacitor-based delay cells in RF and BB domains. The FD receiver is implemented in a standard 65nm CMOS process and operates from 100MHz - 1GHz with gain tunability of 15-38dB, noise figure of 5.4dB, and power consumption of 31mW. The canceler delay cells have delays ranging from 0.2ns-1.1ns in the RF domain, and 10ns-75ns in the BB domain, while consuming 25.5mW and 6.5mW respectively. These large tunable delays perform FIR-filtering based cancellation, enabling 30-35dB integrated SI cancellation over 20MHz on top of an off-the-shelf ferrite circulator when terminated by a dipole antenna (isolation of 22dB), and can handle TX power of up to +9dBm. Under SIC, the RF and BB cancelers degrade the RX noise figure by 1.1dB and 0.8dB respectively.