Achieving 1 mu m pixel pitch display for electronic holography

Holographic display is known as the most realistic 3D display by creating real 3D image in front of observer. But there are tremendous technical hurdles in realizing electronic hologram. It is required to achieve very small pixel pitch SLM (spatial light modulator) for realizing electronic hologram using flat panel display. All the components of the unit pixel should be carefully redesigned and improved to maintaining same performance in spite of reduction of pixel pitch. The size of hologram image depends on the size of SLM. Therefore, the resolution of the SLM increases very fast as the reduction of pixel pitch in SLM. The driver chip and architecture should be developed to manage the large number of pixels with high speed. Novel unit pixel design for achieving 1 mu m pixel pitch will be presented. VST (vertically stacked transistor) structure will be introduced. In VST structure, the driving TFT is stacked on the data line. VST structure has the merits for reducing horizontal pixel pitch without introducing expensive high-definition lithography tool. The technology compatible with 0.5 mu m critical dimension can be used for fabrication of 1 mu m pixel pitch SLM. Alternative structure for achieving small pitch pixel is the adopting VTFT (vertical channel thin film transistor). VTFT means that the channel direction is vertical to SLM plane. The footprint of VTFT is very small, for required area is only the overlap region of active layer and source/drain layer. Cross-talk between adjacent pixels can interfere the rotation of LC molecule. This phenomenon will be very critical for accurate phase modulation for 1 mu m pixel pitch SLM. Novel concept for reducing cross-talk will be also presented with experimental results.