A PFC Converter With Low Ripple and High Efficiency

This paper proposes a buck compensated Flyback PFC circuit structure. This power factor correction circuit can significantly improve the dynamic response speed of the circuit while reducing or even eliminating the double power frequency ripple. The overall circuit consists of two parts: the power factor correction part and the ripple compensation part. The power factor correction circuit uses a Flyback structure as the main circuit, and a buck circuit is connected in series at the output to perform ripple compensation. The result is low output voltage ripple and fast dynamic response. Experimental prototype tests show that this structure of the PFC circuit has approximately the same power factor value as the traditional power factor circuit, but it can greatly reduce the output power double ripple, and the circuit response speed is compared with the single-stage PFC structure There is a significant improvement, and the output efficiency is higher than the two-stage PFC circuit.