A 16b 4GSPS Two-Times Interleaved DAC with INL <= +/- 2.9LSB HAI DONG(1,a) , ZONGMIN WANG, YING KONG, XINMANG PENG

A two-times interleaved DAC in a standard 65nm CMOS technology is presented with a data-clock frequency of 4GHz with INL < +/- 2.9LSB. Since two DACs are placed in parallel, their output current goes to the DAC multiplexer, which alternatively connects one DAC to the output, and the other one to an identical dummy output. The two-times interleaved DAC with quartered switches increases the overall data of two times and reduces the complexity of the design effectively while suppressing the non-idealities.