SpiderWeb - High Performance FPGA NoC

In this paper we introduce SpiderWeb, a new methodology for building high speed soft networks on FPGAs. There are many reasons why greater internal bandwidth is an increasingly important issue for FPGAs. Compute density is rapidly growing on FGPA, from historical precisions such as single precision floating point, to the massive parallel low precision operations required by machine learning inference. It is difficult for current FPGA fabrics, with designs developed using standard methods and tool flows, to provide a reliable way of generating wide and/or high speed data distribution busses. In contrast, SpiderWeb uses a specific NoC generation methodology which provides a predictable area and performance for these structures, with area and speed accurately known before compile time. The generated NoCs can be incorporated into large, complex designs, implemented with standard design flows, without compromising routability of the system.