A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD

In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented. The proposed PLL employed a nonmodified digital standard cell library, and enable fast design migration to other processes. To minimize the reference spur, a self-clocked nonoverlap update scheme is proposed to reduce the reference spur caused by digital logic clocking. Besides, a slope-balanced fully s...