Correction to “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS” [Jul 15 1722-1735]

IEEE Journal of Solid-State Circuits（2015）

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摘要

Presents corrections to the paper, “A 0.41 pJ/bit 10 Gb/s hybrid 2 IIR and 1 discrete-time DFE tap in 28 nm-LP CMOS,” (Shahramian, S.) IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722–1735, Jul. 2015.

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关键词

CMOS integrated circuits,Decision feedback equalizers,Intersymbol interference

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