Enabling 3 D Integration Through Optimal Topography

In a 3D stacked IC, through-silicon vias (TSVs) are utilized to interconnect dies vertically. In one common TSV practice, via-first TSVs directly connect the first metal layer of a die and the top metal layer of the die above it. However, the landing pads on the first metal layer, due to their large area and presence of features with widely varying sizes, may result in serious topographic errors after chemical-mechanical polishing. These errors result in cumulative effects in up interconnect layer processing steps, thereby causing yield and performance problems. In this paper, we analyze the impact of TSV landing pads on topography and present a technique to minimize it. We first show that traditional fill methodology is inefficient due to large metal density variations. After selecting best fill possible through conducting design of experiments (DOEs), we run CMP simulations on another DOE to find the impact of TSV to TSV pitch on final topography. Finding a minimum pitch from this experiment, we apply force-directed TSV separation during placement. We achieve 24% ∼ 36% improvement in topography variation with only 0.5% ∼ 2.0% wirelength increase. The improvements presented herein will enable manufacturability of 3D circuits with reduced topographic variations.