Design Space Exploration of a multi-core JPEG

This paper presents the design space exploration of a multi-core implementation of the JPEG algorithm using the Embedded System Environment (ESE). ESE is a tool-set, which enables multi-core system design by high-level modeling of both the hardware platform and software application. In order to define an application model for ESE, sequential JPEG code written in C was partitioned and translated into concurrent processes, which communicate via abstract channels. The application model is then mapped onchannels. The application model is then mapped on the system platform captured as a graphical netlist consisted out of SW and HW cores, buses and buffers. ESE provides means for automatic translation of these models to Transaction Level Models (TLM) in order of seconds. Highspeed TLM simulation was used to identify possible bottlenecks and evaluate different design options for both HW and SW partitioning of the JPEG algorithm application. The obtained experimental results have shown that such approach may find a good solution regarding specific design constraints in a very short time.