Quantifying the Capacity Limitations of Hardware Transactional Memory

Hardware transactions offer a performance advantage over software implementations by harnessing the power of existing cache coherence mechanisms which are already fast, automatic, and parallel. The source of superior performance, however, is also the root of their weakness: existing implementations of hardware transactions abort when the working set exceeds the capacity of the underlying hardware. Before we can incorporate this nascent technology into high-performing concurrent data structures, it is necessary to investigate these capacity constraints in order to better inform programmers of their abilities and limitations. This paper provides the first comprehensive empirical study of the “capacity envelope” of HTM in Intel’s Haswell and IBM’s Power8 architectures, providing what we believe is a much needed understanding of the extent to which one can use these systems to replace locks.