A 100-kS/s 8.3-ENOB 1.7- $\mu\hbox{W}$ Time-Domain Analog-to-Digital Converter

A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11-μm CMOS process with a 0.127-mm2 active silicon area. The TDADC consumes 1.7 μW from a 0.6-V supply voltage.