Reconfigurable Manycore System

An approach for designing the reconfigurable computing systems in FPGA is proposed, which is based on mapping synchronous data flow graphs to a manycore system. The reconfiguration is performed by switching data flows and exchanging the instruction sets of the processor cores. To implement the processor elements of such a system, a 16bit RISC-processor core is developed, which has small hardware costs and a configurable instruction set.