2 A 2 . 2 GHz 7 . 6 mW SubSampling PLL with − 126 dBc / Hz In-Band Phase Noise and 0 . 15 psrms Jitter in 0 . 18 μ m CMOS

A clock with low phase-noise/jitter is a prerequisite for high-performance ADCs, wireline and optical data links and radio transceivers. This paper presents a 2.2GHz clock-generation PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. The PLL does not need frequency divider in locked state and achieves a low in-band phase noise values at low power.