Reed-Solomon decoder IP core

The Reed-Solomon decoder IP core is a highly versatile core generator for creating hardware Reed-Solomon decoder circuits suitable for high speed decoding of the ubiquitous Reed-Solomon Forward Error Correction (FEC) code. This code is used in a wide variety of data storage and transmission applications, such as the Compact Disc, DVD, various kinds of magnetic storage, digital subscriber lines and satellite communications. The core generator is a Java application generating highly comprehensible, standard, deviceand technology-independent VHDL code ready for consumption by industrial FPGA synthesis tools or ASIC processes, while also being suitable for educational use. Generated cores meet the requirements of various standards that specify Reed-Solomon codes, including ATSC, CCSDS1, DVB, IESS-308 and Intelsat channel coding modes.