ALU Designs for Power and Speed Optimization in the 21 st Century

The development of ALUs has aided the by optimizing efficiency and power reduction. Optimizing performance requires novel ideas that will enhance old ones. ALU designs are dissected throughout this paper to compare different designs that have developed over time. The metrics used are datapath width, ITRS Technology node, Execution time per ALU, and Power. Examples of minimizing number of gates and area used will show a significant reduction to power usage. The Baugh-Wooley MAC will prove this below. The examples used in this paper start from the year 2002 to present day, the impact of pipelining has greatly improved the efficiency of ALU designs. Keywords—Throughput, ALU, Power, Adder, CMOS, Clocks, Optimization, Low Power