Reliability and performance of optimised

This study compares the performance and reliability of classical complementary metal-oxide-semiconductor (CMOS) gates with Schmitt trigger (ST) ones. The ST hysteresis, caused by the added positive feedback transistors, improves the design static noise margin (SNM) and offers noise immune operation. Hence, ST-based circuits are expected to operate more reliably than the ones implemented using classical CMOS. Although many research papers have been focused lately on using ST design concepts for implementing more reliable static random access memory (SRAM) cells, significantly less work was devoted to the application of ST concepts in the combinatorial logic domain. Moreover, available research on ST-based logic gates had only focused on the low-voltage/power applications range. The authors are going to look at the whole voltage range and performance spectrum to compare and understand not only the SNMs and the power consumption (at different frequencies and voltage levels) but also the delay and the power-delay-product of ST-based logic gates. These will be compared with classical CMOS as well as with optimally sized CMOS and ST-based logic gates. This study should give a clear picture of the potential advantages ST could offer for combinatorial logic in advanced CMOS technology nodes and of their application range.