Trends in ultra fast silicon trackers

This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC. The detectable range has been greatly increased to 14 bits with the ring structure. A 1-ps resolution was achieving with 2D Vernier architecture. Utilizing the 2nd order ΔΣ modulators (SDM) and a 2D spiral arbiter array, the proposed TDC greatly mitigates the quantization errors introduced by digitally controlled delay cells and the intrinsic arbiter line folding errors associated with the 2D array topology. The measured maximum DNL/INL are 0.41/0.79ps with ΔΣ linearization. A prototype TDC chip fabricated in 130nm CMOS technology achieves a conversion rate of 10 MS/s while consumes 2.4 mW power. Keywords— TDC, resolution, detectable range, linearization, INL, DNL, ΔΣ modulation, quantization error.