Thermal Modelling of 3 D Stacked DRAM with Virtual Platforms

Heterogeneous 3D integrated systems with Wide-I/O DRAMs are a promising solution to squeeze more functionality and storage bits into an ever-decreasing volume. Unfortunately, with 3D stacking the challenges of high power densities and thermal dissipation are exacerbated. In order to provide a framework for exhaustive design space explorations, we developed an advanced Transaction Level (TLM) based virtual platform that models the performance, power and thermal behaviour of a 3D-integrated MPSoC with Wide-I/O DRAMs in detail.