Hardware / software codesign of a pattern recognition system with on-chip learning

In this paper, we propose a designing method for a hardware implementable pattern recognition system with on-chip learning. The architecture proposed herein takes advantage of distinct modules for controlling the peripherals of the development board and for data processing as forward and backward stages of the propagation and learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The entire proposed concept relies on the idea that a FPGAs implementable neural network can be reached only by choosing the predesigned generic blocks and to set the parameters of the network into a pop-up window.