Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory

The scheduling of data access plays a prominent part in a memory-based fast Fourier transform (FFT) processor. In this article, a conflict-free data-access scheme is proposed and applied to implement a radix- $2^{k}$ FFT processor with the computing parallelism being the power of 2. The proposed FFT module exploits single-port RAMs to retain the area efficiency, and it has the following hardware-friendly features. First, the memories are merged into four banks under the arbitrary computing parallelism, which helps to circumvent the complicated data-routing circuit. Second, the parallelism of the input/output (I/O) data can be enlarged to the internal computing parallelism, which accelerates the data update and enhances the throughput capability. Furthermore, the concurrent I/O operation that overlaps the storage of the FFT input with the supply of FFT output in the same memory sets is allowed, which minimizes the memory occupation for the management of continuous data flow. Based on the testing on the field-programmable gate array (FPGA) and ASIC implementation using the SMIC 40-nm CMOS technology, it is demonstrated that the proposed FFT processor can offer high throughput and simultaneously achieve remarkable area and power efficiency.