Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers

2020 IEEE 38th VLSI Test Symposium (VTS)(2020)

引用 0|浏览8
暂无评分
摘要
A reconfigurable wrapper provides the flexibility for a core test to utilize different bandwidths of test access mechanism (TAM) at different test time points. By using reconfigurable wrappers, the lower bound of total test application time can be achieved. However, since reconfigurable wrappers attempt to utilize TAM bandwidth as fully as possible, they often consume a lot of routing resources. In advanced technology nodes, routability has become a critical and difficult issue. In this paper, based on reconfigurable wrappers, we present the first work that studies the correlation between grid-based TAM wire routing and test scheduling. Our objective is to derive a feasible grid-based TAM wire routing solution with the minimum total test application time. Compared with previous works, the main advantage of our approach is that it can resolve the grid-based TAM wire routing congestion problem during test scheduling. Benchmark data show that our approach can effectively and efficiently minimize the total test application time under grid-based routing congestion constraints.
更多
查看译文
关键词
Layout,Routing Congestion,SoC Testing,Test Scheduling,Test Time Minimization
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要