Tileable Monolithic ReRAM Memory Design

Non-volatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint sub-arrays that leave the bulk of transistors underneath the sub-arrays vacant. This permits placing the memory system over other logic. We propose a tileable, centralized ReRAM design over a large last level cache. This design takes advantage of ReRAMs unique characteristics while still providing flexibility to designers.