Energy-performance characterization of CMOS/magnetic tunnel junction (MTJ) hybrid logic circuits

The explosive growth of the semiconductor industry over the past decade has been driven by the rapid scaling of complementary metal-oxide-semiconductor (CMOS) technology. However, the evolutionary CMOS scaling has resulted in physical constraints and will likely become very difficult at and below the 22-nm node. As the physical gate length of CMOS device is getting closer to the physical constraint [1], many short channel effects arises, resulting in very high device leakage and performance instability, which greatly deteriorate the energy efficiency and functionality of CMOS circuits. The high leakage can not only cause loss of information during unexpected power supply interruptions (volatility), but can also give rise to high standby power, creating difficulty in implementing designs for low-power applications.In order to extend the scaling and to reduce the energy dissipation for ultralow-power applications, various emerging approaches for realizing new electrical switches with a variety of nano-scale technologies have been suggested in the ITRS roadmap [2]. However, CMOS technology will continue to advance along lines as prescribed in the next decade and to lead technology innovations despite its increasing scaling problems [2]. Thus, in short term, people will keep looking for new switches that supplement CMOS, are CMOS-compatible and can support low-power operation. Spin-based devices are among the candidates for these goals, as the energy needed to change an electron spin is much smaller than what