An Adaptive Multitasking Superscalar Processor

For CPUs, the design tradeoffs between high-performance computing and low-power consumption can be made a run-time decision instead of being statically built into each system. The ability to dynamically conFigure a system for either purpose, depending on characteristics of the user application, can empower a system to better conserve energy while meeting application timelines. This paper presents an Adaptive Multitasking Superscalar Processor (AMSP) that allows its internal two pipelines to be reconfigured on the fly, through an instruction issue policy that avoids all pipelining stalls and a logic design that enables the two-way pipeline to be dynamically coupled or decoupled, allowing the CPU to operate, on the fly, as either a dual-issue superscalar processor catering to high performance or a scalar processor catering to low-power consumption, depending on what the overall system needs, without incurring any overhead when switching between the two operating modes. When operating in the low-power mode, the architecture design also provides some limited redundancy support, so that the CPU can continue to operate even when some of its functional stages were damaged. We have used two benchmarks, Dhrystone and Coremark, to validate the performance and functionality of our CPU design, where our design has boosted the average Instructions Per Cycle (IPC) of the dual-issue CPU by up to 1.717.