An FPGA-based Hardware Acceleration For Key Steps of Facet Imaging Algorithm

SKA (Square Kilometer Array) is an under-construction radio telescope with the largest observation aperture, and also it is an international science project that requires the participation and cooperation of multiple countries and organizations. SKA scientific data processing is an application with huge amount of data and extremely high computation performance requirement, and has strict energy consumption restrictions. The high performance on data I/O rate determine s cloud computing to be a feasible solution to such a strict computing restriction. However, the traditional processor of cloud computing even if the most sophisticated super computer can not meet the requirements. Therefore, it is necessary to explore a new acceleration structure. FPGA (Field-Programmable G ate Array) is a computation platform that combines the advantages of high-level parallelization and low power consumption. Therefore, heterogeneous cloud computing structure of CPU + FPGA becomes available to solve SKA's data processing requirements. This paper mainly discusses the high efficiency FP GA-based hardware acceleration of the key algorithm Facet i n SKA. There are two time-consuming parts during the Facet procedures-Phase Rotation and Gridding. Firstly, a pipeline acceleration structure designed for Phase Rotation algorithm is determined. The simulation and tests on FPGA are done to confirm the acceleration result of our design and it shows the performance is 32.07 times of the result running on software. Then determined an efficiency optimized core computation acceleration structure of loop expansion + pipeline for Gridding, and the designed system simulation is done to confirm the performance of our structure. The result shows that the acceleration ratio is 5.48 compared to the result tested on software.