Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-memory Computational Platform
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits(2020)
摘要
This article presents a method for analyzing the parasitic effects of interconnects on the performance of the STT-MTJ-based computational random access memory (CRAM) in-memory computation platform. The CRAM is a platform that makes a small reconfiguration to a standard spintronics-based memory array to enable logic operations within the array. The analytical method in this article develops a methodology that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin. Finally, the method determines the maximum allowable CRAM array size under various technology considerations.
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关键词
Transistors,Resistance,Logic gates,Integrated circuits,Wires,Capacitance,Logic arrays
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