A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel

Current 5G chip solutions have the focus on delivering the extreme: an end-to-end experience of 5ms latency and a minimum of 1Gb/s data rate. This is what seems to be the requirement for the vast market of 5G smartphones. However, 5G applications cover three orders of magnitude of latency (2000ms-2ms) and five orders of magnitude of data rate (10kb/s to 1Gb/s). Hence, how can we build solutions that require only a small window of latency-rate parameters. E.g., for factory automation, we can expect 10-100Mb/s at a maximum of 5ms end-to-end latency to address the needs.We introduce a scalable hardware/firmware solution to this problem, which we named "Kachel". This requires writing parameterized firmware only once and allows its automatic remapping onto scalable hardware. The hardware scales at two levels of hierarchy: At node-level, a new memory interface allows for multiple processors as well as accelerators to efficiently share common memory sub-blocks such that energy-expensive copying of memory becomes obsolete. At the MPSoC-level, we propose a tiled method with an advanced router and NoC management. This platform scales at both levels of hierarchy to address the 5G requirement of interest. It is ready for other applications stretching beyond 5G.