Investigation of advanced FDSOI CMOS devices for analog/mixed signal applications

A comparison of CMOS devices with best in class noise behavior and low power consumption for analog/mixed signal applications has been achieved by extensive TCAD simulations. The intrinsic gain gm/ID of FDSOI transistors was optimized by several process adjustments. An advanced bulk device with improved noise behavior was used as a reference and different bias conditions were simulated. With certain layer optimizations the gm/ID was improved by 50% in the low power regime. An additional improvement up to 50% has been achieved by biasing the FDSOI device in double gate mode (DGM).