An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS Process

Y. Zha,Loïc Zahnd,Jiang Deng,David Ruffieux,Komail M. H. Badami,T. Mavrogordatos, Y. Matsuo,Stéphane Emery

2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)（2019）

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摘要

This paper presents an industry-ready PVT-robust 12-bit 1 MS/s untrimmed SAR ADC IP operating from 0.5/0.9V supply voltage for a sub-threshold sensor interface. The ADC exploits Fujitsu's 55 nm Deeply Depleted Channel (DDC) technology to dynamically regulate the bulk voltage of the NMOS and PMOS transistors to compensate for the PVT variations. This dynamic regulation of the the bulk voltage is enabled by a technology-assisted replica-biasing based design strategy. This enables a PVT-robust comparator operation up to 14MHz frequency from a 0.5V supply voltage to allow the ADC to achieve 68 dB±1.1dB SNDR and 88 dB+3.5dB THD over P(SS,TT,FF) - V(0.45V to 0.55V) - T(-40°C to 90°C) variations at an average 12fJ/CS efficiency at 1/10 ^th of the sampling frequency.

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关键词

PVT-robust comparator operation,Deeply Depleted Channel CMOS process,PMOS transistors,technology-assisted replica-biasing based design strategy,dynamic regulation,PVT variations,sub-threshold sensor interface,untrimmed SAR ADC IP,voltage 0.45 V to 0.55 V,temperature -40.0 degC to 90.0 degC,size 55.0 nm,voltage 0.5 V,voltage 0.9 V,frequency 14.0 MHz,word length 12 bit

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