A 4.8pj/b 56gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.

Gain Kim,Lukas Kull,Danny Luu,Matthias Braendli,Christian Menolfi,Pier Andrea Francese,Hazar Yueksel,Cosimo Aprile,Thomas Morf,Marcel A. Kossel,Alessandro Cevrero,Ilter Özkaya,Hyeon-Min Bae,Andreas Burg,Thomas Toifl,Yusuf Leblebici

A-SSCC（2019）

Cited 7|Views141

Key words

frame-based PAM-4 modulation,PAM-4 symbols,CP taps,PAM-4 frame window,DMT symbol,DMT signal equalization,discrete-time Fourier transform,frequency-domain equalizer,DSP data-path,channel delay spread,FinFET,cyclic prefix,ADC-based PAM-4 wireline receiver data-path,size 14.0 nm,noise figure 19.0 dB,frequency 14.0 GHz,power 270.0 mW,bit rate 56 Gbit/s

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