22.2 an 8.5gb/s/pin 12Gb-Lpddr5 SDRAM with a Hybrid-Bank Architecture Using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd Generation 10nm DRAM Process
2020 IEEE INTERNATIONAL SOLID- STATE CIRCUITS CONFERENCE (ISSCC)（2020）
Key words
duty-cycle correction,1-tap DFE receiver,active-resonant load,read-write DQ valid windows,WCK-always-on mode,current gain,command-based WCK control scheme,high density memories,power-optimization,bus based RDBI AC,ADAS,advanced driver assistance system,handheld artificial intelligence,deep-sleep mode,DVFS,dynamic-voltage-frequency scaling,internal data copy,mobile devices,bit rate 7.5 Gbit/s to 8.5 Gbit/s,storage capacity 8 Gbit,storage capacity 12 Gbit,current 36.0 mA,size 10.0 nm,time 118.0 ps,voltage 1.05 V,skew-tolerant scheme,speed-boosting techniques,hybrid bank architecture,bank-mode,hybrid-bank architecture,2nd generation DRAM process,energy efficiency,low-power schemes,LPDDR4X,LPDDR5 SDRAM
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