An optimal algorithm for allocation, placement, and delay assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
ASPDAC '11: 16th Asia and South Pacific Design Automation Conference Yokohama Japan January, 2011, pp. 503-508, 2011.
Satisfying clock skew constraint is one of the most important tasks in the clock tree synthesis. Moreover, the task becomes much harder to solve as the clock tree is designed under multiple power mode environment, in which the voltage applied to some design module varies as the power mode changes. Recently, it is shown that adjustable del...More
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