Design of a cyclic column-parallel ADC for Monolithic Active Pixel Sensor

This paper describes a 5-bit cyclic column-parallel ADC for Monolithic Active Pixel Sensor. The column-parallel ADC combines the dedicated sample phase and the signal conversion phase into a single phase. Moreover, it has a high tolerance to the offset of the comparators in the ADC by generating 1.5 bit in every stage. Each column-parallel ADC covers a small area of 100 mu m x 200 mu m, consumes 4.5mW at 3.3V supply and provides the sampling rate of 10 MS/s with the dynamic range of 1000mV. The results show that the ADC has a signal-to-noise and distortion ratio (SNDR) of 28.47 dB. Its DNL and INL are -0.039/0.055 LSB and -0.048/0.095 LSB, respectively.