First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

S. -W. Chang,P. -J. Sung,T-Y. Chu,D. D. Lu,C. -J. Wang,N. -C. Lin,C. -J. Su,S. -H. Lo, H. -F. Huang, J. -H. Li,M. -K. Huang,Y. -C. Huang,S. -T. Huang,H. -C. Wang, Y. -J. Huang, J. -Y. Wang, L. -W Yu, Y. -F. Huang,F. -K. Hsueh,C. -T. Wu,W. C. -Y. Ma,K. -H. Kao,Y. -J. Lee,C. -L. Lin,R. W. Chuang,K. -P. Huang,S. Samukawa,Y. Li,W. -H. Lee,T. -S. Chao,G. -W. Huang,W. -F. Wu,J. -Y. Li,J. -M. Shieh,W. -K. Yeh,Y. -H. Wang

IEEE Conference Proceedings（2019）

Cited 67|Views102

Key words

CMOS inverter,GAA CFETs structure,3D-IC applications,6T-SRAM cells,vertically stacked gate-all-around complementary FETs,voltage transfer characteristics,3-dimensional CFET inverters,2-dimensional CMOS,reduced gate delay,drain electrodes,vertically stacked source electrodes,lithographic steps,post metallization treatments,VTCs,butterfly curves,pMOS threshold voltage symmetry,nMOS threshold voltage symmetry,input parasitic capacitance,power consumption,junctionless transistors

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