Three-Layer BEOL Process Integration with Supervia and Self-Aligned-Block Options for the 3 Nm Node

V. Vega-Gonzalez,C. J. Wilson,B. Briggs,S. Decoster,J. Versluijs,A. Lesniewska,S. Paolillo,R. Baert,H. Puliyalil,J. Bekaert,E. Kesters,Q. T. Le,C. Lorant, O. P. Varela,L. Teugels,N. Heylen,Z. El-Mekki,M. van der Veen,T. Webers, H. Vats,L. Rynders,M. Cupak,J. Uk-Lee,Y. Drissi, L. Halipre,A. -L. Charley,P. Verdonck,T. Witters, S. V. Gompel,Y. Kimura,N. Jourdan,I. Ciofi,A. Gupta,A. Contino,G. Boccardi,S. Lariviere, L. Dupas,B. De-Wachter,E. Vancoille,F. Lazzarino,M. Ercken,P. Debacker,R. Kim,D. Trivkovic,K. Croes,P. Leray, L. Dillemans, Y. -F. Chen,Z. Tokei

2019 IEEE International Electron Devices Meeting (IEDM)（2019）

Cited 17|Views67

Key words

self-aligned-block options,three-layer BEOL process,tip-to-tip,resistance modulation,high aspect ratio supervias,metallization schemes,T2T reliability tests,line-to-line reliability tests,self-aligned block technique,accelerated stress conditions,three-layer BEOL process integration,electromigration tests,full barrier-less Ruthenium dual-damascene metallization,size 3.0 nm,size 21.0 nm,time 140.0 hour,Ru

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