Punch-Through And Dibl Effects Exposing Nano-Node Soi Finfets Under Heat Stress
2019 IEEE 26TH INTERNATIONAL SYMPOSIUM ON PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA)(2019)
摘要
Through the electrical measurement plus the heat stress to enhance the existed or latent defects of FinFETs in the nano-node process flow is a useful metrology. This method not only effectively and timely provides the mapping analysis in a whole wafer, but the sensed data may be correlated to the process variation and optimization in statistical analysis. Besides the common electrical characteristics in ON/OFF current, the punch-through and drain-induced barrier lowering (DIBL) effects like a pair of detectors are good tools to probe the channel integrity. More process parameters of V-T implantation related to these two effects are discussed.
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关键词
Punch-through, DIBL, FinFET, Heat stress, Channel integrity, implantation
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