An error-tolerant serial binary full-adder via a spiking neural P system using HP/LP basic neurons

We present an implementation of an improved adder via a spiking neural P system. Our adder processes arbitrary length binary numbers, and thus, is suitable for cryptographic applications. Due to the use of dual-rail logic, the adder is also error tolerant. We present the implementation concept, as well as a simulation model in System-C.